ASIC Digital Designer

You will work among a team of engineers and technicians to: Design, simulate, and verify the digital architecture of the next-generation ASIC front-end. Prepare RTL designs for tapeout using open-source EDA flows, including floorplanning and physical design preparation. Support post-fabrication bring-up, system characterisation, and functional/performance validation. Collaborate closely with analogue, verification, and SoC integration teams to ensure seamless system-level compatibility.

At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive. Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success.

• Hands-on experience with open-source ASIC EDA flows (Yosys, OpenROAD, LibreLane, etc.) from RTL to GDSII.

• Experience with floorplanning, constraint definition, and physical design preparation for tapeout.

• Post-tapeout prototype bring-up and hardware debugging experience is advantageous.

• Active contributions to open-source hardware projects or EDA toolchains are advantageous.

• Experience developing SoC submodules is advantageous.

• HDL design and simulation in VHDL, Verilog, or SystemVerilog.

• Good team player: collaboration skills across analogue, digital, verification, and SoC teams.

• Proficiency in Git, CI/CD pipelines, and automated verification workflows.

• Knowledge of RISC-V architecture.

• Familiarity with mixed-signal integration and digital interface protocols.

• Comfort with Linux-based development environments and scripting for automation (Python, Bash, etc.).

• Spoken and written English, with a commitment to learn French.

• You are a national of a CERN Member or Associate Member State.

• By the application deadline, you have a maximum of two years of professional experience since graduation in Electronics (or a related field) and your highest educational qualification is either a Bachelor's or Master's degree.

• You have never had a CERN fellow or graduate contract before.

• Applicants without University degree are not eligible.

• Applicants with a PhD are not eligible.