CERN Organisation Européenne pour la Recherche Nucléaire
Digital ASIC Designer
📍 Geneva
Rolle und Verantwortlichkeiten
Analyse application requirements across CERN's accelerator complex and particle physics detector systems to define technical specifications for the microcontroller ASIC. Contribute to the architecture, design, and validation of a radiation-tolerant microcontroller ASIC implemented in 65 nm or 28 nm CMOS technology. Support the definition of the SoC architecture, including the selection and configuration of an appropriate RISC-V processing core. Design, integrate, and validate peripheral IP blocks within the CERN SOCRATES framework. Apply fault-tolerant design methodologies, including triple modular redundancy (TMR) and single-event upset (SEU) mitigation techniques. Participate in design verification activities and physical implementation, from RTL development through to tapeout. Contribute to post-silicon testing, characterisation, and validation following chip fabrication.
Team / Beschreibung
At CERN, the European Organization for Nuclear Research, we are pushing the frontiers of science and technology. Our groundbreaking work brings together not only physicists but also a diverse range of professionals from engineering, technical, scientific, and administrative fields. Together, we foster an environment where innovation and collaboration thrive. Every day, we face exciting new challenges and opportunities to contribute to cutting-edge research that shapes our understanding of the universe. We meet these challenges through the diverse perspectives within our teams, ensuring every contribution is valued and driving our shared sense of inclusion and purpose. Diversity is a core value of CERN since its foundation, and it remains central to our mission and continued success.
Qualifikationen und Fähigkeiten
Strong understanding of digital logic design.
Solid experience with digital IC design and RTL development (Verilog/SystemVerilog).
Familiarity with standard ASIC design flows (synthesis, place and route, timing closure).
Knowledge of RISC-V architecture and its ecosystem.
Experience with microcontroller-based embedded systems development, including firmware programming in C and peripheral interfacing.